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--Archivo: data_memory.vhd 		                        --
--Fecha de creación: 3/02/2011				            --
--Última fecha de modificación: 11/02/2011		        --
--Diseñador: Typson Sanchez				                --
--Diseño: Memoria de Datos Entrelazada.			        --
--Propósito: Almacenamiento y Acceso a Datos del 	    --
--	Procesador FFT					                    --
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entity data_memory is
  port(
    DATA_i         	        : in  std_logic_vector(3 downto 0);
    WRITE_ENABLE_i   	    : in  std_logic;
    ADDRESS_i        	    : in  std_logic_vector(5 downto 0);
    COUNTER_i               : in  std_logic_vector(1 downto 0);
    CLK_i            	    : in  std_logic;
    DATA_o                  : out std_logic_vector(3 downto 0)
  );
end data_memory;

architecture structural of data_memory is

  component mux
    port (
        a : in  std_logic_vector (3 downto 0);
	    b : in  std_logic_vector (3 downto 0);
	    c : in  std_logic_vector (3 downto 0);
	    d : in  std_logic_vector (3 downto 0); 
    	s : in  std_logic_vector (1 downto 0); 
    	o : out std_logic_vector (3 downto 0)
  	); 
  end component;

  component vector_element
    port (
    DATA_I                 : in  std_logic_vector(3 downto 0);
    WRITE_ENABLE           : in  std_logic;
    CLK                    : in  std_logic;
    ADDRESS		           : in  std_logic_vector(5 downto 0);
    DATA_O                 : out std_logic_vector(3 downto 0)
  	); 
  end component;

  component decoder_3
    port ( 
        SEL    : in  std_logic_vector (2 downto 0);
        outlet : out std_logic_vector (3 downto 0)
    );
  end component;

  signal decoder_sel: std_logic_vector (2 downto 0);
  signal decoder_out: std_logic_vector (3 downto 0);
  signal data0: std_logic_vector (3 downto 0);
  signal data1: std_logic_vector (3 downto 0);
  signal data2: std_logic_vector (3 downto 0);
  signal data3: std_logic_vector (3 downto 0);

begin
   
   decoder_sel(2) <= WRITE_ENABLE_i;
   decoder_sel(1 downto 0) <= COUNTER_i;

   decoder0 : decoder_3 port map(
     SEL   => decoder_sel,
     outlet => decoder_out
   );

   vector_element0: vector_element port map(
     DATA_I         => DATA_i,
     WRITE_ENABLE   => decoder_out(0),
     ADDRESS        => ADDRESS_i,        
     CLK            => CLK_i,
     DATA_O         => data0
   );

   vector_element1: vector_element port map(
     DATA_I         => DATA_i,
     WRITE_ENABLE   => decoder_out(1),
     ADDRESS        => ADDRESS_i,        
     CLK            => CLK_i,
     DATA_O         => data1
   );

   vector_element2: vector_element port map(
     DATA_I         => DATA_i,
     WRITE_ENABLE   => decoder_out(2),
     ADDRESS        => ADDRESS_i,        
     CLK            => CLK_i,
     DATA_O         => data2
   );

   vector_element3: vector_element port map(
     DATA_I         => DATA_i,
     WRITE_ENABLE   => decoder_out(3),
     ADDRESS        => ADDRESS_i,        
     CLK            => CLK_i,
     DATA_O         => data3
   );

  mux0 : mux port map(
    a => data0,
    b => data1,
    c => data2,
    d => data3,
    s => COUNTER_i, 
    o => DATA_o
  );

end structural;
